1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a test circuit to conduct tests on memories.
2. Description of the Related Art
A system that is formed by integrating memories and logics on a single semiconductor chip, such as a so-called system LSI (large scale integrated circuit) is known. In the system LSI, a plurality of function blocks (cores or macros) such as memory and logic circuits are provided on a semiconductor chip. Another system LSI having a DRAM (dynamic random access memory) macro using a DRAM as a memory (referred to as an embedded DRAM hereinafter) has been developed. The DRAM macro represents a block that functions as a memory and includes a memory cell array, a decoding circuit and a sense amplification circuit.
The embedded DRAM usually has several tens of bits to hundred and several tens of bits as the width of a bus in the semiconductor chip. To test the embedded DRAM, test data output from the embedded DRAM is minimized by a test circuit because no test environment is adapted to the embedded DRAM even though the test data is output from the DRAM through pads corresponding to the bus width or the DRAM has no space enough to arrange such a large number of pads.
If an embedded DRAM has one DRAM macro whose internal bus is 128-bit wide, it is not favorable for the chip area or the test environment as described above in order to output 128-bit test data to the outside. The bit width of input/output (I/O) data is therefore converted to 8 bits through a test circuit.
In the above case, a 16-bit internal bus is assigned to one I/O. In data write mode, test input data written by a tester or the like is converted in serial-parallel by the test circuit. In data read mode, test output data read out of the DRAM macro is converted in parallel-serial by the test circuit. In other words, a plurality of internal buses are connected in parallel to a single I/O.
In order to test an embedded DRAM having a plurality of DRAM macros, test data is written to/read from the DRAM macros at the same time. Test time can be shortened accordingly.
In an embedded DRAM having two DRAM macros that differ in address space, the DRAM macros cannot be tested simultaneously under the same conditions. For example, when the row address space and column address space of a first DRAM macro are both larger than those of a second DRAM macro, the entire address space of the second DRAM macro is completely accessed before that of the first DRAM macro is completely done. In this case, the first and second DRAM macros will vary in mismatch such as refresh time intervals and in conditions of electrical stress on the macros.
When the first and second DRAM macros are tested at the same time, if the space of the row address of the second DRAM macro is half that of the row address of the first DRAM macro, the test time of the second DRAM macro will be half that of the first DRAM macro. The second DRAM macro is not accessed before the test of the first DRAM macro is completed but caused to pause. This pause is not caused in the first DRAM macro.
While the bit lines of the first DRAM macro subject to electrical stress, those of the second DRAM macro does not subject thereto. In a multi-macro product having macros that differ in address space, data cannot simultaneously be written to or read from the macros.
As related art, a method of testing a plurality of memory cores simultaneously is disclosed (see Jpn. Pat. Appln. KOKAI Publication No. 2002-157900).